How to Make Sense of the Memory Controller on a Motherboard

Memory controllers operate a logical format reading and writing dynamic random access memory (DRAM). They also perform a "refresh" operation. By sending a current through the entire device, the DRAM has the system's most up to date data.

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This is important because without constant refreshes DRAM capacitors leak their charge within a fraction of a second and will lose the data written to it. But the underside is that even though this has the potential to increase the system's performance, it locks the microprocessor into a specific type of memory. This in turn forces a chip or motherboard redesign that will support newer memory technologies.

There are many memory-controller features that need to be considered during the design phase. You have access priority of the data and error checking and correcting (ECC) operations. There is also read-write support, as well as byte-write implementations. Furthermore, because data can also fall out of order, there must be some access support for such data. In addition, you also have FIFO options, latency, and bandwidth elements that must be considered to make the memory controller fully functional.

Additional information on RAM can be found at Random Access Memory - How Computer Memory Works

Multiplexers and demultiplexers make the reading and writing to DRAM possible. They select the correct row and column address from the memory unit. These are the inputs for the multiplexer circuit. The demultiplexer on the DRAM unit can select the correct memory location and return the data to that location. A multiplexer is the preferred choice device in order to reduce the number of wires required to construct the system.

The memory controller uses a bus to communicate with the memory cell. This width comes from the number of parallel circuit lines available in order to electronically communicate with the memory cell. There is a variety of bus widths available.

The bus width available for a memory controller can range from 8-bit in older systems, to 512-bit in more complicated systems and video cards. These are usually activated as four 64-bit, simultaneous, memory controllers operating in parallel. In some cases, though, some bus widths are designed to operate in a manner where two 64-bit memory controllers access a 128-bit memory device.

One of most important developments in the past 10 years has been how how memory speeds have improved. In a decade the speeds went from 133 Mhz SDR DIMM RAM to 1333 Mhz DDR3 DIMM RAM. However, CPU speeds have gotten even faster. Nevertheless, as fast as RAM speeds have improved there has been a latency that has not been overcome. This affects the speed of the CPU.

One way to improve the latency, (or reduce it) is with a process called granularity. Here, the process involves splitting one 128 bit channel in two 64 bit channels. This is "gang" mode.

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In ganged mode, there is a 128 bit wide logical DIMM that maps the first 64 bits on the physical DDR channel A and the last 64 bit on DDR channel B. The physical address space, in other words, is interleaved between the two DIMMs in 64 bit steps

In unganged mode, each DCT can operate independently with its own 64 bit wide address space. So the processor can be programmed to interleave the single, physical address space on the two normalized address spaces associated with the two memory channels.

The position that AMD takes is to enable unganged mode to get the benefits from increased parallelism. Note that some CPU models, the 8 and 12 core Magny Cours G34 processors, can only use the unganged mode. This method is one of several that allow the CPU to have faster access to memory.

Image Source: Ilsistemista.net

A memory controller is a circuit that controls memory. This circuit can be located in one of two ways, either inside the motherboard chipset, which is also known as MCH or Memory Controller Hub (located in the northbridge chip), or inside the CPU. The one used will depend on the generation of the processor you have. Motherboard memory controllers make the data transfer between RAM devices and the CPU faster. Bus width, and the ganged and unganged modes can contribute to the speed that the memory transfers the data to the CPU. CPU starvation is avoided, or at least reduced.

Additional information can be found in Learn About the Motherboard Northbridge.

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