The Future is Shanghai
Information about Phenom II may be sketchy at his point, but information about Shanghai is not. This is key, because unlike Intel, which tends to lead with consumer product and follow up with server platforms later, AMD follows a reverse pattern, releasing server-based products first. What this means is that Shanghai Opertrons are basically Phenom IIs, in the same way that Core 2s are basically Xeons. Or at least, that is the theory.
One of the largest changes made with Shanghai is the expansion of overall cache to 8MB, 6MB of which is L3 cache. AMD uses exclusive cache, which means each level of cache is responsbile for its own data. In contrast, the cache on Intel processors in inclusive, which means that the data on higher levels of cache are replicated on the L3 cache. That means all of Shanghai's 6MB L3 cache can be utilized, though it can cause snooping, where one core starts looking for things in another core's cache. Another interesting feature is SmartFetch, which dumps the L2 and L1 cache associated with a core into the L3 cache when that core is not needed. This overcomes a traditional problem with Phenom's exclusive cache system - if the data in a cache isn't replicated in the L3 cache, then a core can't be put completely to sleep, because the cache associated with that core has to remain active. Other improvements include the move to the faster HyperTransport 3 interconnect (although that is not enabled in the earliest Shanghai Opterons) and an increase in supported memory frequency from 667Mhz to 800Mhz.
The results are positive, but not overwhelmingly so. Early reviews of Shanghai Opterons are, of course, focused on server applications, and as such they do not provide a completely accurate picture of how the Phenom II will perform. That said, the results show that Shanghai Opterons are slightly behind to even with the performance of Core 2 Xeons on a clock-for-clock basis. They do best with programs that take advantage of their superior architecture, and fall behind in benchmarks that are bound by compute power. This is in line with what we've come to expect from Phenoms.