The Random access memory, called "RAM" in short, is also known as the primary memory of the computer. RAM is considered as random access because of the fact that it can access any memory cell directly with the knowledge of the point of intersection of the row and column at that cell.
The counter part of RAM is called the Serial Access Memory or SAM. SAM stores the data as a series of memory cells. These memory cells can only be accessed in a serial fashion. If the required data is not found in a memory location, then the other locations are traversed sequentially until the data is reached. SAM is best suited for memory buffers. This is because in memory buffers the data is stored in the order of their arrival or in the order in which the data can be used. Data in RAM can be accessed in any order.
One may imagine the technology behind the architecture of the memory chips. It is quite similar to that of the microprocessor where in integrated circuits millions of transistors and capacitors are employed to build up the memory chip. The most common form of the computer memory is called the Dynamic Random Access Memory or DRAM. In the DRAM a transistor and capacitor form the major circuitry element and the combination forms a memory cell. In DRAM the memory cell is used to represent a single bit of data. The data bit is usually a 0 or a 1 and is stored in the capacitor part of the memory cell. The transistor component is used as a switch for the entire circuit. The transistor is used to control the circuit in a manner such that the state of the capacitor is changed in order to read the data contained in the memory cell.
The capacitor can be compared to a small bucket that is capable of storing some charges in the form of electrons. In order to store a 1 in the memory cell, the capacitor bucket is filled with the electrons. To store 0 in the memory cell, the capacitor bucket is emptied. The problem with the capacitor bucket is that it is "leaky." It means that the capacitor will lose all its charges within a few millisecond of time. This causes a major setback that has to be met when DRAM is used. This problem is solvable. The remedy to make the DRAM work is that the capacitor in the memory cell has to be recharged every cycle by either the CPU or the memory controller itself before the discharge. This process can be accomplished by the memory controller by performing a read and write operation on the content of the capacitor. This refresh operation happens for every microsecond, and this refresh operation is where dynamic RAM gets its name. The process of refreshing creates a latency and slows down all the memory operations.