The X58 is also Intel’s first chipset to use Quick Path Interconnect (QPI) to allow the CPU to speak to an Input/Output Hub, which communicates with the PCIe cards and southbridge. See the picture first picture below, from a slide used in a briefing by Intel’s Stephen L. Smith. Not shown in the picture, but worth noting, the southbridge (ICH10) is still connected by DMI. If the IOH sounds a lot like the old northbrige without the memory controller to you, you’re not alone; the terms are beginning to be used together or interchangeably.
Intel is talking about a “two-chip” solution with Nehalem, where the CPU works in concert with a single bridge. The second picture, another of Mr. Smith’s slides, shows how this will work for the mainstream Nehalem platform (dubbed Ibex Peak) due in the second half of ’09. Note that Ibex will not use QPI, but DMI to connect the CPU and I/O system. As far as Core i7 and the X58 on which it runs, though, the IOH looks very much like a northbridge. See the third picture, this time a slide from a presentation (TDPS001, p. 25) by Patick K. Ng at the 2008 Taipei Intel Development Forum.
Without getting bogged down in the details (Intel has a cool little video explaining things here) the biggest difference between the QPI and FSB, other than QPI not having to handle traffic between the CPU and memory, is that where the FSB can handle about 12.8 GB/s of data in one direction at a time, the QPI can handle that much in each direction at once. The effect of that benefit is dependent on how well balanced the QPI traffic to and from the CPU is, but, combined with getting the memory hooked directly to the CPU, the improvement should be dramatic.
We will look at the X58 chipset and Core i7 performance in a couple articles. The next article will look at some of the motherboard choices available for the platform.