X58 Tylersburg: Big Changes to Motherboards Are Coming

Intel has been doing things the same way for a long time. Anytime the CPU had to talk to something, it got on the Front Side Bus over to the northbridge, which could be thought of as a roundabout (ed.- traffic circle) with exits leading to the memory, PCI-E cards, and, via Direct Media Interface (DMI), the southbridge (a roundabout in its own right; with exits for hard drives, USBs, etc). Chipsets with North and South Bridges are explained here.

This lead to two big problems. For one the FSB only goes in one direction at once. If the CPU asks for something from memory, once it starts coming back, the CPU can’t say "hold on I want something else" or wait I need to tell the graphics card something" until the memory has said its piece.

The other issue is that the PCI-E, memory, and southbridge data all waiting to pull into the roundabout create traffic jams, or, returning to computing parlance, bottlenecks.

Also, the new Core i7 chips run on the LGA1336 sockets. Usually a new socket is a pretty big deal, but it actually is over shadowed by the other new features in the X58 chipset.

AMD would argue it isn’t that new, but Intel is going with a memory controller right on the CPU for the first time in recent, uhh… memory. If the CPU wants to deal with the memory, no more taking the FSB to the northbridge to get there, they are now directly connected.

Nehalem is a DDR3-only architecture, at least as far as the X58 is concerned. The most exciting change brought by X58 involving memory, except it being connected directly to the CPU, is that it uses a triple-channel, instead of the traditional dual-channel system.

As opposed to buying a pair of memory sticks, you buy a kit of three. The big memory makers are all rolling out these triple channel kits presently.

This increases the theoretical maximum bandwidth by 50%. Actual gains will be lower than that, but should still be significant: Much as dual channel memory doubles the theoretical maximum transfer rate, not the memory’s performance in general; but still increases the latter noticeably.

The X58 is also Intel’s first chipset to use Quick Path Interconnect (QPI) to allow the CPU to speak to an Input/Output Hub, which communicates with the PCIe cards and southbridge. See the picture first picture below, from a slide used in a briefing by Intel’s Stephen L. Smith. Not shown in the picture, but worth noting, the southbridge (ICH10) is still connected by DMI. If the IOH sounds a lot like the old northbrige without the memory controller to you, you’re not alone; the terms are beginning to be used together or interchangeably.

Intel is talking about a “two-chip” solution with Nehalem, where the CPU works in concert with a single bridge. The second picture, another of Mr. Smith’s slides, shows how this will work for the mainstream Nehalem platform (dubbed Ibex Peak) due in the second half of ’09. Note that Ibex will not use QPI, but DMI to connect the CPU and I/O system. As far as Core i7 and the X58 on which it runs, though, the IOH looks very much like a northbridge. See the third picture, this time a slide from a presentation (TDPS001, p. 25) by Patick K. Ng at the 2008 Taipei Intel Development Forum.

Without getting bogged down in the details (Intel has a cool little video explaining things here) the biggest difference between the QPI and FSB, other than QPI not having to handle traffic between the CPU and memory, is that where the FSB can handle about 12.8 GB/s of data in one direction at a time, the QPI can handle that much in each direction at once. The effect of that benefit is dependent on how well balanced the QPI traffic to and from the CPU is, but, combined with getting the memory hooked directly to the CPU, the improvement should be dramatic.

We will look at the X58 chipset and Core i7 performance in a couple articles. The next article will look at some of the motherboard choices available for the platform.